This invention relates generally to digital signal processing and more particularly to a system and method for reducing leakage current in dynamic circuits with low threshold voltage transistors.
In the art of digital signal processing, the speed of dynamic circuits is becoming increasingly important. Thus, in order to improve the speed of these circuits, one technique has been to use low threshold voltage transistors. However, disadvantages associated with using low threshold voltage transistors include an increased leakage current for the circuit while in standby mode.
Previous attempts to solve this leakage problem have included using a combination of low threshold voltage transistors and standard threshold voltage transistors in a circuit. However, this previous solution is less than optimum as it has failed to provide as great an increase in speed as possible due to the use of standard threshold voltage transistors which are slower than the low threshold voltage transistors.
Thus, the previous solution to the leakage problem with low threshold voltage transistors counter-acts the increased speed provided by the low threshold voltage transistors, which was the original reason for their use.
In accordance with the present invention, a system and method for reducing leakage current in dynamic circuits with low threshold voltage transistors are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods. In particular, a dynamic circuit with low threshold voltage transistors is disclosed that provides reduced leakage current without a decrease in speed.
In one embodiment of the present invention, a reduced-leakage current dynamic circuit is provided that includes a logic circuit, a pre-charge transistor, and a standby transistor. The logic circuit is coupled to an internal output node. The logic circuit includes a plurality of logic transistors having a low threshold voltage. The pre-charge transistor is coupled to the internal output node. The pre-charge transistor is operable to provide a pre-charge voltage at the internal output node and has a standard threshold voltage. The standby transistor is coupled to the internal output node. The standby transistor is operable to provide a standby voltage at the internal output node.
Technical advantages of the present invention include providing an improved dynamic circuit with low threshold voltage transistors. In particular, a pre-charge transistor has a standard threshold voltage, while logic transistors have low threshold voltages. As a result, pre-charging (which is not a time-critical operation) is accomplished with a standard threshold voltage transistor, and discharging (which is a time-critical operation) is accomplished with low threshold voltage transistors. Accordingly, the standard threshold voltage transistors may be used without reducing speed.
Other technical advantages of the present invention include reducing the leakage current. In particular, an internal output node is discharged through a standby transistor during standby mode. Additionally, the dynamic circuit is placed in standby mode while the clock is high. As a result, during standby mode, the path from the internal output node to an opposite power rail is blocked by a standard threshold voltage transistor which reduces leakage current.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.